1. Field of the Invention
This invention relates generally to telecommunications systems. More particularly, the present invention relates to time-division-multiplexers (TDMs).
2. State of the Art
Known TDM systems are used for multiplexing information present on a plurality of input channels onto a single output or aggregate data channel. This multiplexing function is generally achieved by the use of a data "frame" to efficiently allocate and combine the incoming data from the input channels into the aggregate channel. An example of a framing algorithm for allocating the data from a plurality of input channels to an aggregate channel is disclosed in U.S. Pat. No. 4,881,224 to Bains, which is hereby incorporated herein by reference in its entirety.
In typical TDM systems of the art, a central processor and a plurality of channel modules are provided. The incoming channels are coupled to the individual channel modules. Each channel module is typically coupled to the central processor via a data bus and an address bus. The central processor generates and contains the framing algorithm. The central processor executes the framing algorithm by communicating with the channel modules. In particular, based on the framing algorithm, the central processor uses the address bus to inform the channel modules as to the particular times they are to place information on a data bus. Thus, the central processor places an address on the address bus, and the channel module at that address is then permitted to place information on the data bus. In bit interleaved multiplexers, the information placed by the channel module onto the data bus is a single bit of information at a time. It will be appreciated that in byte interleaved multiplexers, when the address of the channel module is indicated, a whole byte of information may be placed onto the data bus.
With the prior art systems, large burdens are placed on the central processor. Not only does the central processor have to supervise the time division multiplexing of data onto the data bus by quickly generating and sending source and destination addresses to the channel modules via the address bus according to the determined framing algorithm, but the central processor typically is utilized to check the status of the various channel modules and to test that they are functioning properly. While at relatively slow speeds these functions may be readily accomplished, at high TDM rates, difficulties arise.